A charge device model (CDM) is often used to simulate charge build-up and electrostatic discharge (ESD) in a packaged integrated circuit device. Generally, the build-up of charge in the packaged integrated circuit device is simulated by applying a voltage between an input-output (I/O) pad of an integrated circuit formed in a semiconductor die of the packaged integrated circuit device and a ground plane external to the packaged integrated circuit device. The electrostatic discharge is simulated by providing a conductive path from the input-output pad to a ground potential and causes a peak current to flow through the input-output pad. Because a sufficiently high peak-current flowing through the input-output pad may cause damage to components of the integrated circuit, reducing the peak electrostatic discharge current is desirable in a packaged integrated circuit device.
Generally, reducing the peak electrostatic discharge current in a packaged integrated circuit device improves electrostatic discharge immunity of the packaged integrated circuit device, but adversely affects other performance characteristics of the packaged integrated circuit device. For instance, reducing the peak electrostatic discharge current in the packaged integrated circuit device may reduce a rate of thermal conduction from a semiconductor die in the packaged integrated circuit device to the ambient environment of the packaged integrated circuit device.
An alternative technique for improving electrostatic discharge immunity of a packaged integrated circuit device involves increasing the number and sizes of components in electrostatic discharge protection circuitry at input and output pads of the packaged integrated circuit device. As a result, the electrostatic discharge protection circuitry consumes additional die area of a semiconductor die in the packaged integrated circuit device. Additionally, capacitive loading increases at the input and output pads of the packaged integrated circuit device, which reduces the speed of signals propagating through the input and output pads.
In light of the above, a need exists for reducing a peak electrostatic discharge current in a packaged integrated circuit device without reducing a rate of thermal conduction from a semiconductor die in the packaged integrated circuit device to the ambient environment of the packaged integrated circuit device. A further need exists for reducing the peak electrostatic discharge current in the packaged integrated circuit device without increasing the area of the semiconductor die consumed by electrostatic discharge protection circuitry in the packaged integrated circuit device.